New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC - Département STIC
Journal Articles Journal of Signal Processing Systems Year : 2024

New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC

Abstract

In this paper, we address the challenge of a real-time solution for the critical detection step in a LTE-advanced (LTE-A) cognitive radio (CR) network implemented using limited computing resources. The detection step is required to identify a free radio channel that can be used to transmit data. We first present two new detectors and their naive implementations on a CR platform running over LTE-A, an orthogonal frequency division multiple access (OFDMA) network. The first detection method is based on the subband’s energy and the second uses both correlation on the cyclic prefix (CP)’s part and the energy of the useful orthogonal frequency division multiplexing (OFDM) signal. We then optimize them to satisfy the low-latency detection constraint on a low-cost embedded board using a ZYNQ XC7Z020 system on a chip (SoC). We use Xilinx Vitis high-level synthesis (HLS) computer-aided design (CAD) tool to design our solutions. Finally we achieve the implementation of a solution that requires less than one OFDM symbol period (70 μs) for a detection system that complies with the worst scenario timing constraint of the LTE-A standard.
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Dates and versions

hal-04705309 , version 1 (23-09-2024)

Identifiers

Cite

Grégoire de Broglie, Louis Morge-Rollet, Denis Le Jeune, Frédéric Le Roy, Christian Roland, et al.. New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC. Journal of Signal Processing Systems, inPress, ⟨10.1007/s11265-024-01932-9⟩. ⟨hal-04705309⟩
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